Network interfaces include physical layer devices that transmit and receive data over a medium. In a 10 gigabit/second (10 Gb) network, the physical layer devices can include a physical coding sublayer (PCS) module that encodes, multiplexes, and synchronizes outgoing symbol streams. The PCS module also aligns, demultiplexes, and decodes incoming symbol streams. In one approach, the PCS module is implemented based on a 10GBASE-X standard in the Institute of Electrical and Electronics Engineers (IEEE) 802.3 specification, which is hereby incorporated by reference in its entirety. The 10GBASE-X standard provides for 4-lane to 4-lane aggregation through the PCS module and specifies an 8-bit to 10-bit (8/10) encoding pattern for each lane. In another approach, the PCS module is implemented based on a 10GBASE-R standard in IEEE 802.3. The 10GBASE-R standard provides for 4-lane to 1-lane aggregation and specifies a 64-bit to 66-bit (64/66) encoding pattern for the single lane of aggregated data. FIGS. 1-6 provide examples of PCS modules according to the 10GBASE-X and 10GBASE-R standards.
Referring now to FIG. 1, the International Organization for Standardization's ISO Open Systems Interconnection (OSI) model 10 includes a physical layer device 12 for transmitting and receiving data over a medium. The physical layer device 12 can employ different architectures for various types of physical media and bandwidth requirements.
Two example 10 Gb architectures are provided at 14-1 and 14-2. First 10 Gb architecture 14-1 is suitable for a single chip or system-on-chip (SOC) implementation of physical layer device 12. A reconciliation layer 16 provides a logical connection between a medium access controller (MAC) and other elements of the physical layer device 12. Reconciliation layer 16 communicates with a PCS module 20 via a 10 Gb media-independent interface (XGMII) 18. PCS module 20 communicates with a physical medium attachment unit (PMA) 22 that includes clock recovery and compensation logic for the incoming symbol streams. PCS module 20 communicates with a physical medium dependant (PMD) sublayer 24 that includes transmitters and receivers (transceivers). A media-dependent interface (MDI) 26 connects PMD 24 to a communication medium 28. MDI 26 can include various fiber-optic and copper connections to medium 28.
The second 10 Gb architecture 14-2 is suitable for use in applications that include chip-to-chip and/or backplane structures. In those architectures the physical layer device 12 is remotely located from the MAC and/or other higher network layers. An XGMII extender 29 allows XGMII 18 to communicate over greater distances. Extender 29 includes a pair of 10 Gb extended sublayer (XGXS) interface devices that connect to respective XGMII 18 interfaces of reconciliation layer 16 and PCS module 20. An extended attachment unit interface (XAUI) connects between the XGXS interface devices and provides 10 Gb communication through four lanes of communication.
Referring now to FIG. 2, a physical layer connection is shown between two network stations that employ the 10GBASE-X standard. The stations include respective PCS module 20-1 and 20-2, referred to collectively as PCS modules 20. PCS module 20 communicates through medium 28, which includes four lanes.
First PCS module 20-1 receives data and idle symbols via four-lane XGMII 18. A substitutor module 30 replaces the idle symbols with specified control symbols and then outputs the data and control symbols onto four lanes 32-1, . . . , 32-4, referred to collectively as lanes 32. The control symbols include alignment symbols /A/, boundary symbols /K/, and disposable symbols /R/. The /K/ symbols represent boundaries of respective data groups. Substitutor module 30 periodically generates the /A/ symbols simultaneously on all lanes 32 with a pseudo-random period. The pseudo-random period satisfies minimum and maximum spacing specifications. Second PCS module 20-2 then uses each group of /A/ symbols to compensate for timing differences between the lanes 32. Substitutor module 30 also adds and deletes the disposable symbols /R/ from each lane 32 to compensate for frequency differences between XGMII 18 and lanes 32.
Each output of substitutor module 30 is eight bits wide. Each lane 32 includes an 8-to-10 bit converter 34 that converts the 8-bit data to the 10-bit format. Bit patterns in the 10-bit format are generated according to an algorithm that maximizes signal level switching across the medium 28. The signal level switching minimizes the risk of developing a DC offset in the medium 28. An output of each 8/10 bit converter 34 communicates with an input of a respective amplifier 36. Each amplifier 36 drives the 10-bit data onto a respective lane of medium 28. Amplifiers 38 communicate the 10-bit data to respective 8/10 bit converters 40 that restore the 8-bit data. The restored 8-bit data leaves respective 8/10 bit converters at different times, i.e. the restored 8-bit data is misaligned due to different propagation delays through each of lanes 32. Lane alignment module 42 realigns the data based on the /A/ symbols that were inserted by substitutor module 30 that are shown in FIG. 3. Lane alignment module 42 communicates the realigned data to an XGMII 18 of second PCS module 20-2.
Referring now to FIG. 3, first and second data diagrams 50-1, 50-2 show the four lanes of data into and out of substitutor module 30. In first data diagram 50-1 idle symbols are represented by blank fields 52. Data is represented by data fields 54 that include data DN, where N represents a serial order of the respective data field. An /S/ symbol in field 56 represents a start of the data. A /T/ symbol in field 58 represents a terminus of the data. A column of the simultaneously-inserted /A/ symbols appear at fields 60 and are used by lane alignment module 42.
Referring now FIG. 4, a physical layer connection is shown between two PCS modules 21 that employ the 10GBASE-R standard. First PCS module 21-1 includes a 64/66 encoder 64 that aggregates the four lanes of XGMII 18 into one lane of data. A scrambler 66 prepares the data for transmission and ensures sufficient transition density. Data from the scrambler 66 is transmitted to a gearbox 68. Gearbox 68 formats data for a serializer/deserializer module (SerDes) 70. Gearbox 68 may include a FIFO buffer. SerDes 70 receives the data from gearbox 68 and transmits it through a single-lane medium 28. A second SerDes 72 receives the data from medium 28 and forwards it to second PCS module 21-2. Second PCS module 21-2 includes a gearbox 74, a descrambler 76, and a decoder 78, which implement the reverse of the transmit process.
Referring now to FIG. 5, a chart shows the formats of 66-bit data blocks that are allowed by 10GBASE-R. Each 66-bit data block includes a 2-bit sync header 82 that is concatenated with a 64-bit block of data 84. Each 64-bit block of data 84 includes 8 bytes that may be data bytes 86 and/or control symbols 88. Bytes labeled with a C, O, S, or T represent control symbols 88. Bytes labeled with a D represent data bytes 86. A 2-bit sync header 82 with a value of 012 indicates that the entire 64-bit block of data 84 is made up of data bytes 86. When the 2-bit sync header 82 has a value of 102, at least one of the control symbols 88 exists among the 64-bit block of data 84.
Referring now to FIG. 6, a transmitter 90 for PCS module 21-1 is illustrated. XGMII 18 provides a data stream of 32-bit words. Encoder 64 processes two words at a time. Encoder 64 outputs an encoded data block 80 that includes sync header 82. Encoded data block 80 is transmitted to scrambler 66. Sync header 82 is used by a receiver to lock onto a data block. Sync header 82 bypasses scrambler 66. Both a scrambled data block and the sync header 82 are input to gearbox 68. Data from gearbox 68 is transmitted to SerDes 70. Scrambler 96 and gearbox 68 operate according to the 10GBASE-R standard.